The invention relates to electrical measurement, and more particularly to an improved phase detector circuit in an error sampled feedback loop.
There is a need in a variety of applications such as sampling-enhanced measurement systems and avionics navigation systems for detecting the phase coincidence or measuring the phase difference between two periodic signals having the same or slightly differing frequencies.
D-type master-slave flip-flops are used conventionally in phase detector applications; however, the fastest commercially available D-type flip-flops do not provide time/phase resolution in the picosecond range.
In a fixed bias sampling gate, the sampling efficiency is a nonlinear function of the input signal amplitude. To minimize the effect of the nonlinearity, the sampling gate is operated in an error sampled feedback loop (ESFL) utilizing highly oversampled (considerably greater than f/2) sequential sampling. The ESFL allows a high speed, but otherwise nonlinear and unstable sampling gate to operate as a comparator/null detector, reduces strobe radiation into the signal line, and improves the sampling efficiency.
It is therefore an object of the present invention to provide an improved circuit for detecting the phase coincidence between two periodic signals.
It is another object of the present invention to provide an improved circuit for measuring the phase difference between two periodic signals.
It is another object of the present invention to provide an improved phase detector circuit operating as an error sampled feedback loop.
Another object of the present invention is to provide an improved tracking sample and hold circuit for detecting phase coincidence with high speed and picosecond resolution.